5.14. Recall the matrix-vector multiplication example with an 8 8, 000,000 matrix. Suppose that doubles use 8 bytes of memory and that a cache line is 64 bytes. Also suppose that our system consists of two dual-core processors. a. What is the minimum number of cache lines that are needed to store the vector y? b. What is the maximum number of cache lines that are needed to store the vector y? c. If the boundaries of cache lines always coincide with the boundaries of 8-byte doubles, in how many different ways can the components of y be assigned to cache lines? d. If we only consider which pairs of threads share a processor, in how many different ways can four threads be assigned to the processors in our computer? Here, we're assuming that cores on the same processor share cache. e. Is there an assignment of components to cache lines and threads to processors that will result in no false-sharing in our example? In other words, is it possible that the threads assigned to one processor will have their components of y in one cache line, and the threads assigned to the other processor will have their components in a different cache line? f. How many assignments of components to cache lines and threads to processors are there? g. Of these assignments, how many will result in no false sharing? | |
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